Dynamic Random Access Memory (DRAM) is widely used in computers and other electronic devices for storing and retrieving digital data. Many such memory devices are JEDEC DDR3-compliant, and others will be JEDEC DDR4-compliant. DDR is an abbreviation for double data rate, which refers to effecting transfers on both the rising and falling edges of the clock signal in order to double the data transfer rate relative to the clock rate. JEDEC is an abbreviation for the Joint Electron Device Engineering Council, which is an independent semiconductor engineering trade organization and standardization body. The JEDEC DDR3 standard is widely followed, as were the earlier DDR1 and DDR2 standards, and the same is expected for the DDR4 and future JEDEC standards. The DDR3 standard permits DRAM chip capacities of up to 8 Gbit (or gigabit, where a Gbit is 1,073,741,824 bits, being two raised to the power of 30, or about one billion).
A DDR3 synchronous DRAM (SDRAM) module includes a number of DDR3 compliant SDRAM chips, which may alternatively be referred to as “dice” or “dies”. Typically, each chip is enclosed in its own ball grid array (BGA) surface-mount package (or fine-pitch ball grid array (FBGA) package), such as an FBGA 78 package (having 78 balls) or an FBGA 96 package (having 96 balls).
In order to achieve higher density, some existing DDR memory devices stack two chips in a single package. However, in such prior art designs, these two chips operate as if they were packaged separately, having separate control lines for each die that are separately connected to the balls of the BGA package. The assembled memory device is then accessible by a processor as if there were two separate components on the board, although both are inside one package.
In DDR3 technology, the memory is activated and selected by four control pins. These contacts are named Chip Select (CS), Clock Enable (CKE), On-Die Termination (ODT) and ZQ calibration (ZQ). CS, CKE and ODT are connected from the memory chip to the CPU. ZQ is connected to ground through a serial resistor. A monolithic memory chip only has one set of these control lines. In the prior art stacked-chip devices however, two sets of control lines are required. They may be called CS0 and CS1, CKE0 and CKE1, ZQ0 and ZQ1, ODT0 and ODT1 as shown in FIG. 1.
Application designers who elect to use such prior art dual die, dual chip select DDR3 components in their products must prepare their board layouts by routing the additional control pins from every DRAM chip to the processor. In practice, such stacked chip components are rarely utilized because the special design requirements make the use of normal single chip select monolithic DRAMs as an alternate assembly more difficult. Yet another issue is that processors often lack the required number of DRAM control lines to connect such stacked chips, rendering it impossible to access further memory ranks.